two years at cornell custom silicon systems wrapped

the goal was easy to say but stupidly hard to pull off: build a battery-powered chip small enough to tag a wild bird, and accurate enough to actually pick up its call.

kestrel

fall 2024, spring 2025

kestrel was our first project, and the first time we took something all the way through tapeout, fabrication, and got back real silicon that actually worked. it’s an 8-bit sar adc, fully differential, built in tsmc’s 180nm process.

sar adcs are kind of the go-to topology when you need something precise and reasonably fast without burning much power. they narrow in on the right value one bit at a time, like playing twenty questions against an analog voltage. kestrel’s job was to take an audio signal, eventually a bird’s call, and digitize it well enough that the frequency content came through intact.

signal flow, at a glance:

vin+ / vin− → sampling switches → cdac (binary-weighted) → comparator → fsm → 8-bit sar output

what came back from the fab

the chip worked, which honestly still feels like a small miracle in analog design, where one unbudgeted parasitic can quietly wreck months of work. here’s what we measured on silicon:

two things jump out here, for pretty different reasons. the enob and linearity numbers are genuinely solid, this chip digitizes cleanly. but the current draw tells a different story. 151 µa measured against ~16 µa simulated is about a 10x gap. tracing that back led to parasitic leakage paths and clock distribution power that just never made it into the simulation budget. that’s the kind of lesson only silicon can really teach you when your schematic has no idea the wires exist.

the best part, though, was proving the whole concept worked end to end. we digitized and reconstructed a scrub jay call through the adc, and the resulting spectrogram clearly showed the bird’s frequency-modulated chirps.

the design choices that made it work

none of this happens without a handful of deliberate tradeoffs made early on:

• binary weighted cdac, no split capacitor. the capacitor dac is basically the heart of any sar adc — it’s what holds and moves the sampled charge during every bit decision. a split capacitor array saves you area, sure, but it adds parasitic capacitance at the split node, and that hurts more than just gain — it wrecks linearity too. since keeping full 8-bit enob wasn’t something we could compromise on, we just went with a plain binary weighted array instead. parasitics still creep in, but now they only cost gain, and gain we can calibrate out. corrupted bits, we can’t.

• imcs switching. this is the algorithm deciding how charge moves on and off the cdac at each step, and honestly it’s one of the biggest levers you have on both capacitor count and energy. imcs gets away with an (n-1)-bit cdac instead of the full array, which roughly cuts both capacitor count and switching energy in half compared to a conventional sar. when your whole chip is supposed to run off a coin cell strapped to a bird, that’s not a small win.

• bottom plate sampling. charge injection from the sampling switches is one of those things that’s easy to ignore right up until it shows up as a dent in your linearity plot. bottom plate sampling makes that injected charge signal-independent, and since kestrel is fully differential, whatever sneaks through just cancels out as common mode instead of corrupting the signal we actually care about.

• double tail comparator with kickback cancellation. the comparator only pulls current when it’s actually making a decision — zero static power otherwise, which we loved. the annoying part with any dynamic comparator is kickback: the regeneration phase kicks charge back onto the inputs and messes with the exact voltage you’re trying to measure. so we added cancellation transistors sized at half the input pair width to fire off an opposing pulse and cancel that out.

after kestrel

fall 2025, spring 2026

once kestrel proved the team could actually tape out a working adc, the obvious next question was how much further this could go. instead of picking one direction, the next phase split into two parallel projects: one chasing speed, one chasing the lowest power possible.

project 1: an adiabatic flash adc

flash adcs are the fastest architecture around. a bank of comparators fires all at once and decodes directly, no bit-by-bit searching. the catch is that speed costs power, since you need a comparator for every possible output level, all running continuously.

adiabatic (charge recovery) logic is a way around that. instead of dumping switching energy into the substrate as heat, it recovers that energy back into a resonant supply. combine that with a flash topology and you’re aiming for a power regime flash adcs have basically never lived in. as far as we could tell, a fully adiabatic flash adc like this hadn’t really been attempted before, which is exciting, but also means there’s no reference design to fall back on when something breaks.

the power budget:

eighty microwatts total, for a 3-bit flash design. that’s roughly 30x lower power than kestrel, though it’s worth saying kestrel is 8-bit and this is 3-bit, so it’s not a perfectly fair comparison. still a striking number for what adiabatic switching buys architecturally.

a few results worth calling out:

• the adiabatic comparator itself hit 4.27 µw average power (ranging 0.99 to 6.67 µw), about 2x better than the double tail comparator from kestrel, which ran around 10 µw. same job, half the energy, because the switching energy gets recycled instead of wasted.
• building this meant designing a full scrl standard cell library from scratch: inverter, nand, nor, all adiabatic. the improvements over regular cmos aren’t subtle. the scrl inverter runs at 1.85 fj per conversion versus 115.77 fj for cmos, a 62x improvement. nand comes in at 3.8 fj vs 125.47 fj (33x), nor at 3.55 fj vs 55.51 fj (15x).
• all of this needs a 4-phase trapezoidal power clock generator, built around an lc tank. the phases had to be really well matched, amplitude asymmetry stayed under 0.002 mv across all four, with phase accuracy within 1%. sloppy clocks would undo everything the adiabatic gates are buying back.
• the digital backend needed a priority encoder to turn the thermometer code comparator outputs into binary, built entirely from the scrl library. it runs in 4 pipeline cycles at about 172 fj per conversion.
• reference generation turned into its own small research problem. the “fully adiabatic” option was a resonant capacitive divider, but it suffered from charge drift and an unstable sampling window in practice. we ended up going with a boring 50 kω resistor divider at 8 µw instead, since it was more accurate and predictable. sometimes the boring answer wins.

why scrl specifically:

there are a handful of adiabatic logic families out there (ecrl, pfal, cal, scrl), and scrl wasn’t a random pick. it’s structurally close enough to regular cmos that the learning curve stayed manageable, it avoids some of the reverse logic paths that complicate the alternatives, and it needs a simpler power clock scheme overall. the trapezoidal clocks specifically ramp slower, which cuts resistive losses during transitions, and the 16-phase staggered structure leaves room to pipeline later.

layout followed a pretty disciplined plan to keep it all manageable: grid-aligned floorplan, metal 2 for cell routing, metal 3 horizontal for the power clock, metal 4 vertical for inter-cell routing, metal 5–6 for vdd/vss stripes. once you’re routing multiple clock phases that need to match tightly, floorplan discipline stops being optional.

project 2: asynchronous sar adc

the second project took kestrel’s synchronous architecture and asked what happens if you just remove the clock from the bit decision loop entirely. a synchronous sar always waits for a clock edge between decisions, whether or not the comparator has actually settled, so you’re constantly paying for worst-case timing margin. an async sar instead triggers each stage the moment the previous one sends a “done” signal, letting it run at the real speed of the analog circuit instead of some conservative clock period.

it’s still an 8-bit fully differential design with imcs switching, but now with a digitally tunable delay line and a custom edge-triggered sr latch to handle the self-timed handshake between stages.

three hard problems, and how we solved them:

• pulse width sensitivity. the first version used a level-triggered “go” signal, and it got inconsistent right around 5 ns pulse widths, which happened to be exactly the timescale this design needed. we ended up building a custom edge-triggered sr latch from scratch, which got rid of the sensitivity completely instead of just patching around it.

• precharge coupling. the comparator’s precharge window (how long it resets between decisions) was originally set implicitly by logic propagation delay, around 6 ns. that’s a problem because propagation delay shifts with process corner, so the window would quietly shrink or grow depending on the fab run. we added a separate delay line path to control precharge independently, which stretched the window from ~6 ns out to ~23 ns and made it corner-independent.

• mixed-signal simulation at scale. at 68,000+ instances, this isn’t something you casually simulate overnight. getting reasonable turnaround meant testing a few different simulation strategies against each other (plain spectre, spectre with parasitic optimization, spectre ms, and a mixed xcelium/spectre ams flow) to find the right balance between accuracy and something that would actually finish before the next design review.